Calculate and compare multiple clock frequencies if the condition met!

SystemVerilog
, ,
9

In reply to ben@SystemVerilog.us:

module tb;
 timeunit 1ns;
 timeprecision 100ps;
        
 logic clkc = 0;
 logic clka = 0;
 logic clkb = 0;
        
 always #5  clkc = ~clkc;
 always #10 clka = ~clka;
 always #20 clkb = ~clkb;
        
 initial #5000 $finish;

 initial begin 
        #150 signal_1 = 0; signal_2 = 1; signal_3 = 1; signal_4 = 1; signal_5 = 1;
        #200 signal_1 = 0; signal_2 = 0; signal_3 = 1; signal_4 = 1; signal_5 = 1;
        #250 signal_1 = 1; signal_2 = 1; signal_3 = 0; signal_4 = 1; signal_5 = 1;
        #300 signal_1 = 1; signal_2 = 1; signal_3 = 1; signal_4 = 1; signal_5 = 1;
        #350 signal_1 = 1; signal_2 = 0; signal_3 = 1; signal_4 = 0; signal_5 = 1;
        #400 signal_1 = 0; signal_2 = 1; signal_3 = 0; signal_4 = 0; signal_5 = 1;
        #450 signal_1 = 0; signal_2 = 1; signal_3 = 1; signal_4 = 1; signal_5 = 1;
        #500 signal_1 = 0; signal_2 = 0; signal_3 = 0; signal_4 = 1; signal_5 = 1;
        $stop ; 
    end 
            
 assertions_module assertions_module_inst(
     .signal_1(signal_1),
     .signal_2(signal_2),
     .signal_3(signal_3),
     .signal_4(signal_4),
     .signal_5(signal_5),
     .clka(clka),
     .clkb(clkb),
     .clkc(clkc)
 );

endmodule