Assertion to measure timing between two signals

SystemVerilog
4

In reply to Anudeep J:
You need to recreate the expected data change using an event based on any data change.
Below is my approach.



/* In this case my clock is not 50% duty cycle. My data is single bit. 
I want to ensure that clk edge is in between the data. If data is changing, i can track the edges, 
the problem comes when it is stable data. Iam confused how to have both these scenarios in single assertion*/
module top; 
    timeunit 1ns/100ps;
    `include "uvm_macros.svh"
     import uvm_pkg::*;
     bit clk=1'b1, data, a, b;
     event e_data;
     let half_p=5ns; 
     let period=10ns; 
     // realtime current_time;
     initial forever begin 
        #2 clk=!clk; 
        #8 clk=!clk;
     end   
     // sync to data. New data_event based of clock period 
     always  @(posedge data or e_data)   begin 
       // current_time=$realtime;
       #period -> e_data; 
     end 
     // You may want to put a band around the expected 1/2 time 
     // e.g., $realtime-t>=half_p -1ns && $realtime-t<=half_p +1ns;  
     property d2clk; 
        realtime t; 
        @(posedge data) (1, t=$realtime)  |=> @(posedge clk) $realtime-t==half_p; 
     endproperty  
     ap_d2clk: assert property(d2clk);  

     property e2clk; 
        realtime t; 
        @(e_data) (1, t=$realtime)  |=> @(posedge clk) $realtime-t==half_p; 
     endproperty  
     ap_e2clk: assert property(e2clk);  
 endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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