Assertion to measure timing between two signals

SystemVerilog
5

In reply to Anudeep J:

Hi Anudeep,

You don’t have to check when data is Not changing, as there wont be any timing violation.
This is true even in silicon.
below check will work for non-50% duty cycle, you have to specify right setup,hold timing. I have used half_clk here…


//parameter half_clk = 5;
 specify 
    $setuphold(data, posedge clk, half_clk,half_clk);
  endspecify