Thanks Ben and Suresh for the replies.
The requirement is to check whether the edge of clk is centre aligned with data or not.
Lets my clock period is 10ns. If my single bit of data is from 0-10ns, my clock edge should be at 5ns, the next clk edge is at 15ns and data between 10ns to 20ns and so on(assuming 50% duty cycle). Iam trying to write an assertion such that it checks clock edge is aligned at 5ns to data.
Thanks
Anudeep