System verilog assertion : timing checks between to signals

Hello,

I am trying to write an assertion which says.
Example
when signal(data_en) is asserted. within 100us signal(data_ack) should be asserted. both the signal are synced to the posedge of clk.

I have tried below code

property clk_p (int time_period);
time current_time;
time final_time;
($rose(data_en),current_time=time) |=> ##[1:]($rose(data_ack) ##0 (time_period<= $time - current_time));
endproperty

some how it didn’t work as expected. $time(right side) didn’t work properly.

all the suggestion are welcome.

Thanks
sumit

In reply to sumit089:

Use realtime and either first_match or the goto oprator. Otherwise, it looks okay.
With the ##[1:$] in the consequent, the assertion can never fail.

 
property clk_p (int time_period);
realtime current_time;
($rose(data_en),current_time=$realtime) |=> 
    ($rose(data_ack)[->1] ##0 (time_period<= $realtime - current_time));
endproperty

property clk_p (int time_period);
 realtime current_time;
  ($rose(data_en),current_time=$realtime) |=>
 first_match(##[1:$]($rose(data_ack))) ##0 (time_period<= $realtime - current_time));
endproperty
 

Ben systemverilog.us

In reply to ben@SystemVerilog.us:

In reply to sumit089:
Use realtime and either first_match or the goto oprator. Otherwise, it looks okay.
With the ##[1:$] in the consequent, the assertion can never fail.

 
property clk_p (int time_period);
realtime current_time;
($rose(data_en),current_time=$realtime) |=> 
($rose(data_ack)[->1] ##0 (time_period<= $realtime - current_time));
endproperty
property clk_p (int time_period);
realtime current_time;
($rose(data_en),current_time=$realtime) |=>
first_match(##[1:$]($rose(data_ack))) ##0 (time_period<= $realtime - current_time));
endproperty

Ben systemverilog.us

Hi Ben,

I am confused with the use of the assignment operator in the second part of the property?
What’s the motive behind that? Is the time-difference stored in the time_period and then used somewhere else in the testbench to check?
But then the question comes, since this is a concurrent property, does the property actually stores a copy of time_period or the changes to it actually affect the global time_periodd variable?

In reply to devil47:

[quote]In reply to ben@SystemVerilog.us:

time_period is an argument being passed to the property. Let’s say that after $rose(data_en)
your requirement states that $rose(data_ack) should occur with 1 us. You pass as argument the value of 1us. The following tests time_period<= $realtime - current_time), or the sm time when data_ack occurs - the time that data_en occurred.

The time_period should be a constant in your case. However, it could be a variable that you dynamically change. That would happen if, for example, your configuration changes, and you then expect different expect delays.

Actually, you generally do not measure the duration between and sigb in ns, but rather in clock cycles. Thus, you should express yu assertion as

 
 $rose(data_en)|=> ##[1:5] $rose(data_ack); 
// If that is the duration 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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