In reply to UVM_LOVE:
The tools are OK. SV has specific zones when in a time step different types of activities are processed. This is needed because a simulator tool computes sequentially but must emulate concurrency. The style used in that link can lead to errors depending on how a tool handles the model, and this is not a violation of 1800. There is nothing in 1800 that specifies in which sequence the following code is handled:
iniital forever #10 a=!a;
initial forever #10 b=!b;
iniital foever #5 ck=!ck;
SVG 1800 has explicit timing regions to prevent this issue. See my answer at
https://verificationacademy.com/forums/systemverilog/understanding-systemverilog-scheduling-better