In reply to ben@SystemVerilog.us:
I summarized that my issue.
Test vector can build-up in Blocking assignment. but assertion result depends on Tool
such as something Tool will work
If a=1 is processed by the simulator BEFORE the (@(posedge clk) a |-> …
the sampled value of “a” is 1. HOWEVER,
If a=1 is processed by the simulator AFTER the (@(posedge clk) a |-> …
the sampled value of “a” is 0, the defaulted value in the declaration.
To prevent assertion result issue depends on the Tool, you recommend that Non-Blocking assignment would use in Test vector.
Am I correctly understand your answer?