Assertion failed with delay operator

SystemVerilog
,
2

In reply to UVM_LOVE:
The application if your test vectors because you are very much dependent on the sequence in which the simulator processes the code. You have:


always #5 clk = ~clk; //clock generation
  //generating 'a'
  initial begin 
        a=1; b=1;

If a=1 is processed by the simulator BEFORE the (@(posedge clk) a |-> …
the sampled value of “a” is 1. HOWEVER,
If a=1 is processed by the simulator AFTER the (@(posedge clk) a |-> …
the sampled value of “a” is 0, the defaulted value in the declaration.
SVG has explicit timing regions to prevent this issue. See my answer at
https://verificationacademy.com/forums/systemverilog/understanding-systemverilog-scheduling-better
The key here is that your test vectors should be applied with a nonblocking assignment (i.e., the <= ). This is the template I use to check assertions. I modify the variables and constraints as needed.


module top;
  timeunit 1ns; timeprecision 100ps;
  `include "uvm_macros.svh"
  import uvm_pkg::*;
  bit clk, a, b, reset_n;
  default clocking @(posedge clk); endclocking
  initial forever #10 clk = !clk;
  initial begin
    $timeformat(-9, 0, " ns", 10);
    $display("%t", $realtime);
  end
  always @(posedge clk) begin
  end

  property p;
    int v;
    @(posedge clk) disable iff (reset_n == 0) a |-> b;
  endproperty

  initial begin
    bit v_a, v_b, v_err;
    repeat (200) begin
      @(posedge clk);
      if (!randomize(
              v_a, v_b, v_err
          ) with {
            v_a dist {
              1'b1 := 1,
              1'b0 := 1
            };
            v_b dist {
              1'b1 := 1,
              1'b0 := 2
            };
            v_err dist {
              1'b1 := 1,
              1'b0 := 15
            };
          })
        `uvm_error("MYERR", "This is a randomize error");
      a <= v_a;
      if (v_err == 0) b <= v_b;
      else b <= !v_b;
    end
    $finish;
  end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
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    Understanding the SVA Engine,
    Verification Horizons - July 2020 | Verification Academy
    Reflections on Users’ Experiences with SVA, part 1
    Reflections on Users’ Experiences with SVA | Verification Horizons - March 2022 | Verification Academy
    Reflections on Users’ Experiences with SVA, part 2
    Reflections on Users’ Experiences with SVA, Part II | Verification Horizons - July 2022 | Verification Academy
    Understanding and Using Immediate Assertions
    Understanding and Using Immediate Assertions | Verification Horizons - December 2022 | Verification Academy
    SUPPORT LOGIC AND THE ALWAYS PROPERTY
    http://systemverilog.us/vf/support_logic_always.pdf
    SVA Alternative for Complex Assertions
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    SVA in a UVM Class-based Environment
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    SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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