Assertion failed with delay operator

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Thank you Ben. (I’m new for SVA)
Actually I’m confused that assertion result will be depended by the EDA simulator and to prevent issue assertions Test vectors have to be used in Non-Blocking( =>).

I’m trying to execute some examples from https://verificationguide.com/systemverilog/systemverilog-assertions/
then this is not good example for me as your recommend.

Actually, I would like to make a test vector as the below


task test;
...
    @(negedge scl);  #(`WAIT) sda = 1;
    @(posedge scl);  #(`WAIT) sda = 0;
    #10;
    for(int i=0; i<4; i++)#(`WAIT) sda = 1;
...