How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock

SystemVerilog
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How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock.

Thanks!

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In reply to Saraswati:

How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock.
Thanks!

Quick response: You need to look at the problem from a different point of view. I see your question as: Given a signal “a” and a clock “clk”, whenever that signal changes state, does it meet the setup and hold requirements?
With this new set of requirements, you can then write assertions,
I am thinking of something like this (unchecked yet)


property p_hold; 
	realtime t; 
	@(posedge clk) ##1 ($changed(a), t=$realtime) |-> @(a) ($realtime-t)>= HOLD_TIME;
// may need a range on that hold time,  I. E,  >=  <= 
endproperty 
property p_setup; 
	realtime t; 
	@(a) (1, t=$realtime) |-> @(posedge clk) ($realtime-t)>= SETUP_TIME; 
endproperty

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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In reply to ben@SystemVerilog.us:

Okay Thank you…I will try to check it.

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In reply to Saraswati:
Other things to keep in mind are the cases when the signal clock is a multiple of the system clock. For example, if signal is clocked at 1/2, or 1/4 the frequency of the system clock (clk) then you can still meet the setup and hold times, but not be be clocked at that frequency. To detect this condition, you’ll need add cover property statements to test that the signal toggles at least once at the posedges of clk.


ap_toggleT: cover property( @(posedge clk) $rose(a)|=> !a);  
ap_toggleF: cover property( @(posedge clk) $fell(a)|=>  a);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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In reply to ben@SystemVerilog.us:

Thanks Ben! It works!

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In reply to ben@SystemVerilog.us:

if signal is clocked at 1/2, or 1/4 the frequency of the system clock (clk) then you can still meet the setup and hold times, but not be be clocked at that frequency. To detect this condition, you’ll need add cover property statements to test that the signal toggles at least once at the posedges of clk.


ap_toggleT: cover property( @(posedge clk) $rose(a)|=> !a);  
ap_toggleF: cover property( @(posedge clk) $fell(a)|=>  a);

[/quote]

I think I have not understood the purpose of this extra check and how to read that check. Here’s the way I read them:

  1. “at every posedge(clk) if ‘a’ rose, then I’d expect ‘a’ to be 0 in the next posedege(clk)”
  2. “at every posedge(clk) if ‘a’ fell, then I’d expect ‘a’ to be 1 in the next posedege(clk)”

In both cases I’m not sure why I want to do that. Would you care explaining even if this thread is a bit old? Thanks a lot.

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In reply to abasili:
I honestly don’t remember what I was thinking, but I was in error on that one.
My apologies. However, to check for stup and hold, SystemVerilog provides the $setuphold system function in 1800’2017 31.3.3 $setuphold and in 31.9.1 Requirements for accurate simulation Example:
$setuphold(posedge CLK, DATA, -10, 20);

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In reply to ben@SystemVerilog.us:

Thanks a lot for your answer (I missed somehow the notification for all these weeks!). Even though the solution to this question cannot be changed, I consider your last response as the real solution to deal with setup/hold.

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In reply to ben@SystemVerilog.us:

In reply to abasili:
[…] to check for stup and hold, SystemVerilog provides the $setuphold system function in 1800’2017 31.3.3 $setuphold and in 31.9.1 Requirements for accurate simulation Example:
$setuphold(posedge CLK, DATA, -10, 20);

I was trying to use $setuphold(posedge(clk), data, 0, 0) to make sure the change occurred on the clock transition, in a pure RTL sim, but actually the standard says: “When both limits are zero, the $setuphold check shall never issue a violation”.

So I guess the initial question remains still unanswered: how do I make sure a signal belongs to a specific clock domain?