How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock

SystemVerilog
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In reply to Saraswati:

How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock.
Thanks!

Quick response: You need to look at the problem from a different point of view. I see your question as: Given a signal “a” and a clock “clk”, whenever that signal changes state, does it meet the setup and hold requirements?
With this new set of requirements, you can then write assertions,
I am thinking of something like this (unchecked yet)


property p_hold; 
	realtime t; 
	@(posedge clk) ##1 ($changed(a), t=$realtime) |-> @(a) ($realtime-t)>= HOLD_TIME;
// may need a range on that hold time,  I. E,  >=  <= 
endproperty 
property p_setup; 
	realtime t; 
	@(a) (1, t=$realtime) |-> @(posedge clk) ($realtime-t)>= SETUP_TIME; 
endproperty

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us