In reply to Saraswati:
Other things to keep in mind are the cases when the signal clock is a multiple of the system clock. For example, if signal is clocked at 1/2, or 1/4 the frequency of the system clock (clk) then you can still meet the setup and hold times, but not be be clocked at that frequency. To detect this condition, you’ll need add cover property statements to test that the signal toggles at least once at the posedges of clk.
ap_toggleT: cover property( @(posedge clk) $rose(a)|=> !a);
ap_toggleF: cover property( @(posedge clk) $fell(a)|=> a);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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