How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock

SystemVerilog
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6

In reply to ben@SystemVerilog.us:

if signal is clocked at 1/2, or 1/4 the frequency of the system clock (clk) then you can still meet the setup and hold times, but not be be clocked at that frequency. To detect this condition, you’ll need add cover property statements to test that the signal toggles at least once at the posedges of clk.


ap_toggleT: cover property( @(posedge clk) $rose(a)|=> !a);  
ap_toggleF: cover property( @(posedge clk) $fell(a)|=>  a);

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I think I have not understood the purpose of this extra check and how to read that check. Here’s the way I read them:

  1. “at every posedge(clk) if ‘a’ rose, then I’d expect ‘a’ to be 0 in the next posedege(clk)”
  2. “at every posedge(clk) if ‘a’ fell, then I’d expect ‘a’ to be 1 in the next posedege(clk)”

In both cases I’m not sure why I want to do that. Would you care explaining even if this thread is a bit old? Thanks a lot.