How do you write an assertion to check that a signal is changing at the clock? that is, output is synchronous to the clock

[user49]

In reply to abasili:
I honestly don’t remember what I was thinking, but I was in error on that one.
My apologies. However, to check for stup and hold, SystemVerilog provides the $setuphold system function in 1800’2017 31.3.3 $setuphold and in 31.9.1 Requirements for accurate simulation Example:
$setuphold(posedge CLK, DATA, -10, 20);