Hi All,
I have 2 signals clock(duty cycle is not 50%) and data(1-bit). I want to check that the clock edge is aligned to the middle of the data. If it is changing continuously, it is easy to measure, but when the data does not change, it is difficult.
How can I write an assertion to check this scenario, when data is changing and also when data is stable?
Thanks,
Anudeep
In reply to Anudeep J:
Draw a timing diagram. An example of measuring time is
https://verificationacademy.com/forums/systemverilog/system-verilog-assertion-timing-checks-between-signals
In reply to ben@SystemVerilog.us:
Hi Ben,
The one which you pointed is for the timing check.
In this case my clock is not 50% duty cycle. My data is single bit. I want to ensure that clk edge is in between the data. If data is changing, i can track the edges, the problem comes when it is stable data. Iam confused how to have both these scenarios in single assertion
In reply to Anudeep J:
You need to recreate the expected data change using an event based on any data change.
Below is my approach.
/* In this case my clock is not 50% duty cycle. My data is single bit.
I want to ensure that clk edge is in between the data. If data is changing, i can track the edges,
the problem comes when it is stable data. Iam confused how to have both these scenarios in single assertion*/
module top;
timeunit 1ns/100ps;
`include "uvm_macros.svh"
import uvm_pkg::*;
bit clk=1'b1, data, a, b;
event e_data;
let half_p=5ns;
let period=10ns;
// realtime current_time;
initial forever begin
#2 clk=!clk;
#8 clk=!clk;
end
// sync to data. New data_event based of clock period
always @(posedge data or e_data) begin
// current_time=$realtime;
#period -> e_data;
end
// You may want to put a band around the expected 1/2 time
// e.g., $realtime-t>=half_p -1ns && $realtime-t<=half_p +1ns;
property d2clk;
realtime t;
@(posedge data) (1, t=$realtime) |=> @(posedge clk) $realtime-t==half_p;
endproperty
ap_d2clk: assert property(d2clk);
property e2clk;
realtime t;
@(e_data) (1, t=$realtime) |=> @(posedge clk) $realtime-t==half_p;
endproperty
ap_e2clk: assert property(e2clk);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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In reply to Anudeep J:
Hi Anudeep,
You don’t have to check when data is Not changing, as there wont be any timing violation.
This is true even in silicon.
below check will work for non-50% duty cycle, you have to specify right setup,hold timing. I have used half_clk here…
//parameter half_clk = 5;
specify
$setuphold(data, posedge clk, half_clk,half_clk);
endspecify
In reply to ssureshgverifier@gmail.com:
From his requirements, it sounds like the clock is derived from the data. He needs to make sure that the data is clocked at midpoint of the cycle. The data may have some jitter caused by transmission lines or other medium, thus the need for a midpoint.
Thanks Ben and Suresh for the replies.
The requirement is to check whether the edge of clk is centre aligned with data or not.
Lets my clock period is 10ns. If my single bit of data is from 0-10ns, my clock edge should be at 5ns, the next clk edge is at 15ns and data between 10ns to 20ns and so on(assuming 50% duty cycle). Iam trying to write an assertion such that it checks clock edge is aligned at 5ns to data.
Thanks
Anudeep