Topics tagged uvm-ral

Topic	Replies	Views	Activity
Re-lock RAL model UVM UVM , uvm-ral	0	555	September 20, 2022
Can I use ">>" on the configure function in RAL model? UVM UVM , uvm-ral	3	608	July 4, 2022
RAL Model Doubts UVM UVM , uvm-ral	15	3359	April 7, 2022
Communication between predictor and RAL model UVM UVM , uvm-ral	0	736	October 27, 2021
Post_predict callback getting call twice in case reg sequence UVM SystemVerilog , UVM , RAL-register-UVM , uvm-ral	1	1031	September 27, 2021
[RAL] Monitoring write and read transactions with a protocol that works in two cycles UVM UVM , uvm-ral	1	1186	July 27, 2021
Does get_reg_by_offset provide the register link if used at the top level reg_map? UVM UVM , uvm-ral	0	635	June 2, 2021
VHDL Slicing in RAL Backdoor Paths - Possible? UVM UVM , uvm-ral , Backdoor_access-HDL-access-methods	1	938	May 18, 2021
Uvm_backdoor and uvm_frontdoor parallel access to a register UVM UVM , uvm-ral	5	2690	March 27, 2021
Reuse constraints in child classes UVM SystemVerilog , UVM , uvm_reg_block , uvm-ral , uvm_ral	1	1068	February 15, 2021
RAL Model register field read/write UVM UVM , uvm-ral , uvm_ral , adapter-register	1	2261	February 10, 2021
Register Modeling UVM UVM , uvm-ral , uvm-backdoor-register-model , UVM-RAL-systemverilog-ralmodelling	10	1875	November 23, 2020
Where to place sample_values() for getting coverage in UVM RAL? UVM UVM , uvm-ral	3	1736	November 17, 2020
UVM RAL on two different interfaces in the system UVM UVM , uvm-ral	0	926	October 19, 2020
Uvm_reg_indirect_data UVM UVM , uvm-ral	1	941	May 11, 2020
How can I test one random registers from each reg block? UVM UVM , Cookbook-Registers , uvm-ral , UVM-bitbash , uvm_ral	3	3521	May 3, 2020
How to handle Unmapped Registers in RAL UVM UVM , uvm-ral , unmapped	0	1220	April 26, 2020
Register Access by 3 interfaces UVM UVM , uvm-ral	7	2588	April 16, 2020
Monitoring of RO Registers in UVM UVM UVM , uvm-ral	3	1579	April 6, 2020
Common RAL method implemetation UVM UVM , uvm-ral , bitslice	0	968	March 20, 2020
UVM RAL Callbacks for modifying number of bits of data transfer (32b AHB) UVM UVM , UVM-callback , uvm-ral , verifcation	8	2508	March 3, 2020
UVM RAL: How to implement common RAL accessed by two different addressing modes UVM UVM , uvm-ral	2	963	January 27, 2020
Reg_block.get_registers(req_q) returns zero UVM UVM , uvm-ral	3	796	October 22, 2019
Address Overlap Issue using Questa Register Assistant Feature UVM SystemVerilog , UVM , UVM-Register-Assistant , uvm-ral	3	1570	September 19, 2019
How to find bugs in DUT using RAL UVM UVM , uvm-ral	2	1274	September 11, 2019
Problem while adding memory in ral model UVM UVM , uvm-ral	0	840	September 11, 2019
Query regarding RAL UVM UVM , uvm-ral	4	1508	September 9, 2019
UVM RAL implementation methodology for large designs UVM UVM , uvm_reg , uvm-ral	0	1214	September 6, 2019
Can we read a CSR in top_tb? UVM UVM , uvm-ral	1	1198	September 5, 2019
Symbol lookup error UVM UVM , uvm-ral	6	1519	August 23, 2019