Hi all,
I try to check backdoor access to all the registers in my reg_block by the uvm_reg_access_seq. The sequence flow: write
via frontdoor and mirror via backdoor, then write via backdoor and mirror via frontdoor.
but there is a problem: read via backdoor works well, but write via backdoor has no effect
(uvm_is_ok but register’s value is not set).
The hdl_path is correct.
result of the sequencse, for example:
UVM_INFO 3045.0ns reporter|RegModel: Wrote register via DPI backdoor: regmodel.COLOR_0.green=0xe3
UVM_INFO 3545.0ns reporter|uvm_reg_map: Reading address 'h4 via map “regmodel.COLOR_0.color_0”…
UVM_INFO 3565.0ns reporter|uvm_reg_map: Read 'hffffff1c at 'h4 via map “regmodel.COLOR_0.color_0”: UVM_IS_OK…
UVM_INFO 3565.0ns reporter|RegModel: Read register via map regmodel.COLOR_0.color_0: regmodel.COLOR_0.green=ffffff1c
UVM_ERROR 3565.0ns /tools/accellera/uvm-1.1d/src/reg/uvm_reg.svh (2889) reporter|RegModel: Register “regmodel.COLOR_0.green” value read from DUT (0x00000000000000000000000000000000000000000000000000000000ffffff1c) does not match mirrored value (0x00000000000000000000000000000000000000000000000000000000000000e3)
any idea?
class ral_block_cold extends uvm_reg_block;
uvm_reg_map color_0;
rand ral_reg_cold_blue blue;
rand ral_reg_cold_green green;
rand ral_reg_cold_purple purple;
function new(string name = "cold");
super.new(name, build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.color_0 = create_map(“color_0”, 0, 4, UVM_LITTLE_ENDIAN, 0);
this.default_map = this.color_0;
this.blue = ral_reg_cold_blue::type_id::create(“blue”,get_full_name());
this.blue.configure(this, null, “”);
this.blue.build();
this.blue.add_hdl_path_slice(“blue”, -1, -1);
this.color_0.add_reg(this.blue, UVM_REG_ADDR_WIDTH'h0, "RW", 0); this.green = ral_reg_cold_green::type_id::create("green",,get_full_name()); this.green.configure(this, null, ""); this.green.build(); this.green.add_hdl_path_slice("green", -1, -1); this.color_0.add_reg(this.green, UVM_REG_ADDR_WIDTH’h4, “RW”, 0);
this.purple = ral_reg_cold_purple::type_id::create(“purple”,get_full_name());
this.purple.configure(this, null, “”);
this.purple.build();
this.purple.add_hdl_path_slice(“purple”, 8, purple.get_n_bits());
this.color_0.add_reg(this.purple, `UVM_REG_ADDR_WIDTH’h8, “RO”, 0);
endfunction : build
`uvm_object_utils(ral_block_cold)
endclass : ral_block_cold
class ral_block_hot extends uvm_reg_block;
rand ral_reg_hot_orange orange;
rand ral_reg_hot_yellow yellow;
uvm_reg_map color_1;
function new(string name = "hot");
super.new(name, build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.color_1 = create_map(“color_1”, 0, 4, UVM_LITTLE_ENDIAN, 0);
this.default_map = this.color_1;
this.orange = ral_reg_hot_orange::type_id::create(“orange”,get_full_name());
this.orange.configure(this, null, “”);
this.orange.build();
this.orange.add_hdl_path_slice(“orange”, -1, -1);
this.color_1.add_reg(this.orange, UVM_REG_ADDR_WIDTH'h0, "RW", 0); this.yellow = ral_reg_hot_yellow::type_id::create("yellow",,get_full_name()); this.yellow.configure(this, null, ""); this.yellow.build(); this.yellow.add_hdl_path_slice("yellow", -1, -1); this.color_1.add_reg(this.yellow, UVM_REG_ADDR_WIDTH’h4, “RW”, 0);
endfunction : build
`uvm_object_utils(ral_block_hot)
endclass : ral_block_hot
class ral_sys_dolphin extends uvm_reg_block;
uvm_reg_map color_0;
uvm_reg_map color_1;
rand ral_block_cold COLOR_0;
rand ral_block_hot COLOR_1;
function new(string name = "dolphin");
super.new(name);
endfunction: new
virtual function void build(); // virtual added by make_regmodel
this.color_0 = create_map(“color_0”, 0, 32, UVM_LITTLE_ENDIAN, 0);
this.default_map = this.color_0;
this.color_1 = create_map(“color_1”, 0, 32, UVM_LITTLE_ENDIAN, 0);
this.COLOR_0 = ral_block_cold::type_id::create(“COLOR_0”,get_full_name());
this.COLOR_0.configure(this, “cold_reg_i”);
this.COLOR_0.build();
this.color_0.add_submap(this.COLOR_0.color_0, UVM_REG_ADDR_WIDTH'h0); this.COLOR_1 = ral_block_hot::type_id::create("COLOR_1",,get_full_name()); this.COLOR_1.configure(this, "hot_reg_i"); this.COLOR_1.build(); this.color_1.add_submap(this.COLOR_1.color_1, UVM_REG_ADDR_WIDTH’h0);
this.add_hdl_path(“reg_dummy_tb.reg_dummy_i”);
endfunction : build
`uvm_object_utils(ral_sys_dolphin)
endclass : ral_sys_dolphin