Wait and @event syntax difference issues

I have hierarchical signal “`HIER.signal[5:0]”, and inside a sequence(which is not allowed but I am doing for ease), I need to look for value transition from zero to non zero before I sample response signal value. I tried many syntax but only work as below and not sure why all other syntax don’t work, even though logically all of them should work.

I am calling transaction and check_signal_task parallel.

Inside a sequence,

fork
  begin
    call_transaction();
  end
  begin
    check_signal_task();
  end
join

Inside a check_signal_task,

  1. Not working,
wait(`HIER.signal == 1);

  1. Not working,
@(posedge `HIER.clk);
wait(`HIER.signal == 1);

  1. Not working,
@(posedge `HIER.clk iff (`HIER.signal[5:0] == '1));

  1. ONLY this is working.
@(posedge `HIER.clk iff (`HIER.signal[5:0] == 1));

Not working, meaning, it is not waiting as it supposed to be waiting.

As I am cautiously optimistic now, don’t want to comment, but I believe below should also work, but I have not tried yet!

@(posedge `HIER.signal);

Can you please explain, such a behavior from different syntax?

Thank you,
Mega

In reply to megamind:

Please use code tags making your code easier to read. I have added them for you.

If you are looking for a non-zero value, you should be using the expression `HIER.signal != 0 and not == 1 (same as 6’b000001) or == '1 (same as 6’b111111). Also, I’m assuming signal is declared as a 6-bit value, and you are not just selecting the lower 6-bits of a larger value.

You didn’t mention if signal was synchronous or asynchronous. If synchronous, you should only be using the clk edge and not wait statements.

In reply to dave_59:

Dave, thank you very much for suggestions and details, it makes sense now.
Sorry I forgot to code tag, and also forgot to mention it is synchronous signal.

If synchronous, you should only be using the clk edge and not wait statements.
Dave , can you please elaborate on this. I was in the impression that I can use wait wherever I want to wait for any signal or any variable conditions?

I am going to do few more experiments to further confirm if I have any question left for your valuable inputs.

In reply to megamind:

Look at the differences in timing of these events

module top;
  bit clk = 1;
  initial repeat(20) #5 clk=!clk; // posedge on 10,20,30,...
  
  bit signal;
  initial begin
    repeat(2) @(posedge clk) signal <= 1;
    repeat(3) @(posedge clk) signal <= 0;
    repeat(2) @(posedge clk) signal <= 1;
  end
  
  always
    @(posedge clk iff (signal)) 
    $display("1 posedge clk signal high at ",$time);
  always
    @(posedge signal) 
    $display("2     posedge signal high at ",$time);
  always begin
    wait(signal)
    $display("3        wait signal high at ",$time);
    wait(!signal) 
    $display("4        wait signal low  at ",$time);
  end
endmodule

In reply to dave_59:

Dave, thank you, syntax and usage for waiting on some sync/async signal is I think clear now. You may please correct me if required.

Also I got the idea about below two,

@(posedge clk iff (signal))

→ this will need signal high in previous clock cycle too.

@(posedge signal)

→ this is simple 0 to 1 transition.

To me this below two sounds equivalent, I thought I can use them alternatively,
1)

@(posedge signal)
wait(signal)

what difference it makes if signal is synchronous or asynchronous? and why it is recommended to use @(posedge signal) for synchronous signals?

I have further follow up questions. Please look at below diagram, I have updated few display messages from your original code and also generated waveform to understand how values look in log and on the waveforms, somehow SIGNAL value is not matching in the log and on the waveform. It will be great if you can help me understand this.

Left hand side is the simulation results. Right hand side bottom is the code and above that is the waveform for clk and signal, where I have marked the time and you can see at time 10ns , signal on the waveform is shown as 1 , and in the log at the same time it shows as 0 . Similar is the case for other timestamps I have highlighted .

In reply to megamind:

You need to go back and edit your post as your image is not visible. A link to EDAPlayground would be much better.

The 2 big differences between event controls @(posedge signal) and wait(signal)

  1. The transition from 0 to 1 must not have already happened for @(posedge signal) when encountering that event control. It really should read as “wait for the next transition to 1”
  2. wait(signal) will not block if signal is already 1. If you have this construct in a loop without any other blocking event controls, you get an infinite 0-delay loop.

So they only behave the same if signal is not 0 at the point when encountering either event control.

When you say that a signal is synchronous, that means you only want to sample its value on a clock edge. You would want to use @(posedge clk iff (signal))

In reply to dave_59:

Thank you Dave, more clear. Image is blur or not at all posted?
I created EDA playground account. This is the link you can refer - Error

Please solve my waveform values related question, I posted in the previous comment.
Any final comments/inputs are welcome. Seems like I have some good understanding now for this topic.

In reply to megamind:

I have one follow up question on this.

When I use,
@(posedge clk iff ((signal1 == 1) || (signal2 == 1)));
How should I know which signal have arrived, signal1 or signal2?

Thank you,
Mega

In reply to megamind:
You can check them immediately following.

In reply to dave_59:

Got it , it worked. Thank you.