In reply to dave_59:
Dave, thank you, syntax and usage for waiting on some sync/async signal is I think clear now. You may please correct me if required.
Also I got the idea about below two,
@(posedge clk iff (signal))
→ this will need signal high in previous clock cycle too.
@(posedge signal)
→ this is simple 0 to 1 transition.
To me this below two sounds equivalent, I thought I can use them alternatively,
1)
@(posedge signal)
wait(signal)
what difference it makes if signal is synchronous or asynchronous? and why it is recommended to use @(posedge signal) for synchronous signals?
I have further follow up questions. Please look at below diagram, I have updated few display messages from your original code and also generated waveform to understand how values look in log and on the waveforms, somehow SIGNAL value is not matching in the log and on the waveform. It will be great if you can help me understand this.
Left hand side is the simulation results. Right hand side bottom is the code and above that is the waveform for clk and signal, where I have marked the time and you can see at time 10ns , signal on the waveform is shown as 1 , and in the log at the same time it shows as 0 . Similar is the case for other timestamps I have highlighted .