In reply to megamind:
Look at the differences in timing of these events
module top;
bit clk = 1;
initial repeat(20) #5 clk=!clk; // posedge on 10,20,30,...
bit signal;
initial begin
repeat(2) @(posedge clk) signal <= 1;
repeat(3) @(posedge clk) signal <= 0;
repeat(2) @(posedge clk) signal <= 1;
end
always
@(posedge clk iff (signal))
$display("1 posedge clk signal high at ",$time);
always
@(posedge signal)
$display("2 posedge signal high at ",$time);
always begin
wait(signal)
$display("3 wait signal high at ",$time);
wait(!signal)
$display("4 wait signal low at ",$time);
end
endmodule