UVM

UVM
3

In reply to samy:

//Sequence item class

class seq_item extends uvm_sequence_item;

//Randomizing the transaction fields

  rand bit in;
       bit out;
       bit [1:0] state;

//Object and utility macros

 `uvm_object_utils_begin(seq_item)
    `uvm_field_int(in,UVM_ALL_ON)
    `uvm_field_int(out,UVM_ALL_ON)
    `uvm_field_int(state,UVM_ALL_ON)
 `uvm_object_utils_end

//Constructor

 function new(string name="seq_item");
   super.new(name);
 endfunction

endclass


//Sequence class

class seq extends uvm_sequence#(seq_item);

//Utility macro

  `uvm_object_utils(seq)

//constructor

 function new(string name="seq");
   super.new(name);
 endfunction

//Body task

 virtual task body();

  repeat(40)
    begin
      `uvm_create(req);
       req.randomize();
      `uvm_send(req);
    end

 endtask

endclass

//Sequencer class

class sequencer extends uvm_sequencer#(seq_item);

//Utility macro

  `uvm_component_utils(sequencer)

//Constructor

 function new(string name="sequencer",uvm_component parent);
   super.new(name,parent);
 endfunction

endclass

//Driver class

class driver extends uvm_driver#(seq_item);

  virtual intf vif; //Virtual Interface handle

//Utility Macro

  `uvm_component_utils(driver)

//Constructor

  function new(string name="driver",uvm_component parent);
    super.new(name,parent);
  endfunction

//Build phase

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(uvm_config_db#(virtual intf)::get(this,"","vif",vif))
      `uvm_info("VIF",$sformatf("virtual interface handle has been set for:",get_full_name(),".vif"),UVM_LOW);
  endfunction

//Run phase

  virtual task run_phase(uvm_phase phase);
    reset;
    forever
      begin
        seq_item_port.get_next_item(req);
        drive();
        seq_item_port.item_done();
      end
 endtask

  task reset;
    wait(vif.rst);
     `uvm_info("INITIATION",$sformatf("Initialization has started"),UVM_LOW);
     vif.in=0;
    wait(!vif.rst);
     `uvm_info("DONE",$sformatf("Intialization is done"),UVM_LOW);
  endtask

//Drive task

  task drive();

     @(posedge vif.clk);
  
        vif.in<=req.in;
        req.state<=vif.state;
        req.out<=vif.out;
       `uvm_info("DRIVER",$sformatf("Input=%d\tState=%2b\tOutput=%d",vif.in,req.state,req.out),UVM_LOW);
        $display($time,"input=%d",vif.in,"State=%2b",vif.state,"Output=%d",vif.out);
  endtask

endclass

//Monitor class

class monitor extends uvm_monitor;

//Virtual Interface handle

  virtual intf vif;

  uvm_analysis_port #(seq_item) pkt_obtained_port;

//Handle to store transaction information

  seq_item trans;

//Utility Macro

  `uvm_component_utils(monitor);

//Constructor

 function new(string name="monitor",uvm_component parent);
   super.new(name,parent);
   trans=new;
   pkt_obtained_port=new("pkt_obtained_port",this);
 endfunction

//Build phase

 function void build_phase(uvm_phase phase);
   super.build_phase(phase);
 if(uvm_config_db#(virtual intf)::get(this,"","vif",vif))
     `uvm_info("VIF",$sformatf("virtual interface handle has been set for:",get_full_name(),".vif"),UVM_LOW);
 endfunction

//Run phase

 virtual task run_phase(uvm_phase phase);
    forever
      begin
        @(negedge vif.clk);

        trans.in=vif.in;
        trans.state=vif.state;
        trans.out=vif.out;
        `uvm_info("MONITOR",$sformatf("Input=%d\tState=%2b\tOutput=%d",trans.in,trans.state,trans.out),UVM_LOW);  
      end
       
        pkt_obtained_port.write(trans);

 endtask

endclass