In reply to Muthamizh:
//Scoreboard class
class scoreboard extends uvm_scoreboard;
//Utility macro
`uvm_component_utils(scoreboard)
uvm_analysis_imp #(seq_item,scoreboard) pkt_obtained_export;
seq_item trans;
//Constructor
function new(string name="scoreboard",uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
pkt_obtained_export=new("pkt_obtained_export",this);
endfunction
//Write function
virtual function void write(seq_item pkt);
$display("Packets received");
pkt.print();
endfunction
endclass
//Agent class
class agent extends uvm_agent;
sequencer seqcr;
driver dri;
monitor moni;
//Utility macro
`uvm_component_utils(agent)
//Constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(get_is_active()==UVM_ACTIVE)
begin
dri=driver::type_id::create("dri",this);
seqcr=sequencer::type_id::create("seqcr",this);
end
moni=monitor::type_id::create("moni",this);
endfunction
//Connect phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(get_is_active()==UVM_ACTIVE)
begin
dri.seq_item_port.connect(seqcr.seq_item_export);
end
endfunction
endclass
//Environment class
class environment extends uvm_env;
agent agnt;
scoreboard sb;
//Utility Macro
`uvm_component_utils(environment)
//Constructor
function new(string name="environment",uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agnt=agent::type_id::create("agnt",this);
sb=scoreboard::type_id::create("sb",this);
endfunction
//Connect phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
agnt.moni.pkt_obtained_port.connect(sb.pkt_obtained_export);
endfunction
endclass
//Test class
class test extends uvm_test;
//Utility Macro
`uvm_component_utils(test)
environment env;
seq seq1;
//Constructor
function new(string name="test",uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env=environment::type_id::create("env",this);
seq1=seq::type_id::create("seq1",this);
endfunction
//Run phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
seq1.start(env.agnt.seqcr);
phase.drop_objection(this);
endtask
endclass
`include "uvm_sd_test.sv"
module tb_top;
bit clk;
bit rst;
//clock generation
always #2 clk=~clk;
//reset generation
initial
begin
rst=1;
#2 rst=0;
end
//Interface instance
intf vif(clk,rst);
//DUT instance
fsm1 DUT(.clk(vif.clk),
.rst(vif.rst),
.in(vif.in),
.out(vif.out),
.state(vif.state));
//Setting configuration database
initial
begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),"*","vif",vif);
$dumpfile("dump.vcd");
$dumpvars;
end
initial
begin
run_test("test");
end
endmodule
interface intf(input clk,rst);
logic [1:0] state; //Indicates the 2 bit states of transition in the fsm
logic in;
logic out;
endinterface
RTL
//RTL for FSM 1001 MEALY OVERLAPPING SEQUENCE DETECTOR
//=======================================================
//Module for the input and output ports
module fsm1(clk,rst,in,out,state);
input clk,rst,in;
output out;
output [1:0] state;
reg [1:0] state,nextstate;
reg out;
//Clock block for resetting and state transition
always @ (posedge clk)
begin
if(rst)
begin
state=2'b00; //The state goes to reset state when reset is 1
end
else
begin
state=nextstate; //next state becomes the current state when reset is 0
end
end
//Always block for state transition
always @(state or in)
begin
case({state,in})
3'b000:begin
nextstate<=2'b00;
out<=0;
end
3'b001:begin
nextstate<=2'b01;
out<=0;
end
3'b010:begin
nextstate<=2'b10;
out<=0;
end
3'b011: begin
nextstate<=2'b01;
out<=0;
end
3'b100:begin
nextstate<=2'b11;
out<=0;
end
3'b101:begin
nextstate<=2'b01;
out<=0;
end
3'b110:begin
nextstate<=2'b00;
out<=0;
end
3'b111: begin
nextstate<=2'b01;
out<=1; //When the sequence is detected output becomes 1
end
endcase
end
endmodule
COMPILE LIST
import uvm_pkg::*;
`include “uvm_macros.svh”
include "fsm1.sv" include “uvm_sd_interface.sv”
include "uvm_sd_seq_item.sv" include “uvm_sd_sequence.sv”
include "uvm_sd_sequencer.sv" include “uvm_sd_driver.sv”
include "uvm_sd_monitor.sv" include “uvm_sd_agent.sv”
include "uvm_sd_scoreboard.sv" include “uvm_sd_environment.sv”
`include “uvm_sd_tbtop.sv”