//Scoreboard class
class scoreboard extends uvm_scoreboard;
//Utility macro
`uvm_component_utils(scoreboard)
uvm_analysis_imp #(seq_item,scoreboard) pkt_obtained_export;
seq_item trans;
//Constructor
function new(string name="scoreboard",uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
pkt_obtained_export=new("pkt_obtained_export",this);
endfunction
//Write function
virtual function void write(seq_item pkt);
$display("Packets received");
pkt.print();
endfunction
endclass
//Agent class
class agent extends uvm_agent;
sequencer seqcr;
driver dri;
monitor moni;
//Utility macro
`uvm_component_utils(agent)
//Constructor
function new(string name, uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(get_is_active()==UVM_ACTIVE)
begin
dri=driver::type_id::create("dri",this);
seqcr=sequencer::type_id::create("seqcr",this);
end
moni=monitor::type_id::create("moni",this);
endfunction
//Connect phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(get_is_active()==UVM_ACTIVE)
begin
dri.seq_item_port.connect(seqcr.seq_item_export);
end
endfunction
endclass
//Environment class
class environment extends uvm_env;
agent agnt;
scoreboard sb;
//Utility Macro
`uvm_component_utils(environment)
//Constructor
function new(string name="environment",uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agnt=agent::type_id::create("agnt",this);
sb=scoreboard::type_id::create("sb",this);
endfunction
//Connect phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
agnt.moni.pkt_obtained_port.connect(sb.pkt_obtained_export);
endfunction
endclass
//Test class
class test extends uvm_test;
//Utility Macro
`uvm_component_utils(test)
environment env;
seq seq1;
//Constructor
function new(string name="test",uvm_component parent);
super.new(name,parent);
endfunction
//Build phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env=environment::type_id::create("env",this);
seq1=seq::type_id::create("seq1",this);
endfunction
//Run phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
seq1.start(env.agnt.seqcr);
phase.drop_objection(this);
endtask
endclass
`include "uvm_sd_test.sv"
module tb_top;
bit clk;
bit rst;
//clock generation
always #2 clk=~clk;
//reset generation
initial
begin
rst=1;
#2 rst=0;
end
//Interface instance
intf vif(clk,rst);
//DUT instance
fsm1 DUT(.clk(vif.clk),
.rst(vif.rst),
.in(vif.in),
.out(vif.out),
.state(vif.state));
//Setting configuration database
initial
begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),"*","vif",vif);
$dumpfile("dump.vcd");
$dumpvars;
end
initial
begin
run_test("test");
end
endmodule
interface intf(input clk,rst);
logic [1:0] state; //Indicates the 2 bit states of transition in the fsm
logic in;
logic out;
endinterface
RTL
//RTL for FSM 1001 MEALY OVERLAPPING SEQUENCE DETECTOR
//=======================================================
//Module for the input and output ports
module fsm1(clk,rst,in,out,state);
input clk,rst,in;
output out;
output [1:0] state;
reg [1:0] state,nextstate;
reg out;
//Clock block for resetting and state transition
always @ (posedge clk)
begin
if(rst)
begin
state=2'b00; //The state goes to reset state when reset is 1
end
else
begin
state=nextstate; //next state becomes the current state when reset is 0
end
end
//Always block for state transition
always @(state or in)
begin
case({state,in})
3'b000:begin
nextstate<=2'b00;
out<=0;
end
3'b001:begin
nextstate<=2'b01;
out<=0;
end
3'b010:begin
nextstate<=2'b10;
out<=0;
end
3'b011: begin
nextstate<=2'b01;
out<=0;
end
3'b100:begin
nextstate<=2'b11;
out<=0;
end
3'b101:begin
nextstate<=2'b01;
out<=0;
end
3'b110:begin
nextstate<=2'b00;
out<=0;
end
3'b111: begin
nextstate<=2'b01;
out<=1; //When the sequence is detected output becomes 1
end
endcase
end
endmodule
COMPILE LIST
import uvm_pkg::*;
`include “uvm_macros.svh”
include "fsm1.sv" include “uvm_sd_interface.sv” include "uvm_sd_seq_item.sv" include “uvm_sd_sequence.sv” include "uvm_sd_sequencer.sv" include “uvm_sd_driver.sv” include "uvm_sd_monitor.sv" include “uvm_sd_agent.sv” include "uvm_sd_scoreboard.sv" include “uvm_sd_environment.sv”
`include “uvm_sd_tbtop.sv”
Can you be more descriptive beyond “My sequence isn’t driving at all”? What output are you seeing? What output do you expect to see? What do you think the issue is? An output transcript with the error(s) you are seeing is very helpful.
One simple issue is that your reset isn’t long enough. Try changing it from #2 to #20.
In reply to Muthamizh:
Can you be more descriptive beyond “My sequence isn’t driving at all”? What output are you seeing? What output do you expect to see? What do you think the issue is? An output transcript with the error(s) you are seeing is very helpful.
One simple issue is that your reset isn’t long enough. Try changing it from #2 to #20.
This is the output am getting now. but if the signals are driven, there should be state transition happening in my output. if you see my dut rtl, u could understand the way state transition happens. And regarding output, it should become 1 when the sequence 1001 is detected. In the waveform also state and output do not show at all. This is my problem.
In reply to Muthamizh:
yes, Reset isn’t long enough. here i am attaching code after increasing reset duration to 20 and it is working as per your expectations.
Link:- Edit code - EDA Playground
Regards,
Mitesh
really, thanks a lot for helping me out. I have been checking this for the past 3 days. It will be very helpful if you are able to help me out with driver and scoreboard. Thank you again
Because, write method from monitor is called outside the forever begin. ideally when, you sampled anything from interface it should be write to analysis port.
please find the link, it is showing packet received messages from scoreboard.
Link:-
In reply to Muthamizh:
Because, write method from monitor is called outside the forever begin. ideally when, you sampled anything from interface it should be write to analysis port.
please find the link, it is showing packet received messages from scoreboard.
Link:- Edit code - EDA Playground
Thank you so much. It is very very helpful. Thanks a lot
In reply to Muthamizh:
Because, write method from monitor is called outside the forever begin. ideally when, you sampled anything from interface it should be write to analysis port.
please find the link, it is showing packet received messages from scoreboard.
Link:- Edit code - EDA Playground
The input of driver and monitor changes. Could you please help me out with that?
Im getting output like this now. the driver and monitor should show the same output. But only the monitor shows the correct output. There is problem with driver clock i guess. but I am not able to identify it. Could you please help me with this?
I have corrected it to this extent. But the driver is displayed after monitor and scoreboard. How to make driver to display before monitor and scoreboard?
I have now included agent configuration and environment configuration files. But it is showing errors, i dont know what those means. Could you please help me out with this?