I have now included agent configuration and environment configuration files. But it is showing errors, i dont know what those means. Could you please help me out with this?
In reply to Muthamizh:
I have now included agent configuration and environment configuration files. But it is showing errors, i dont know what those means. Could you please help me out with this?
Error: ** while parsing file included at uvm_sd_allfiles.sv(14)
** at uvm_sd_agent.sv(35): Invalid type ‘fsm_agent_config’. Please check the type of the variable ‘ag_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(14)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_agent.sv(48)
** at uvm_sd_agent.sv(48): (vlog-2730) Undefined variable: ‘ag_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(14)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_agent.sv(48)
** at uvm_sd_agent.sv(48): (vlog-2730) Undefined variable: ‘ag_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(14)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_agent.sv(48)
** at uvm_sd_agent.sv(48): (vlog-2730) Undefined variable: ‘ag_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(14)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_agent.sv(48)
** at uvm_sd_agent.sv(48): (vlog-2730) Undefined variable: ‘ag_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(14)
** at uvm_sd_agent.sv(69): (vlog-2730) Undefined variable: ‘fsm_agent_config’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** at uvm_sd_environment.sv(35): Invalid type ‘fsm_env_config’. Please check the type of the variable ‘env_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_environment.sv(47)
** at uvm_sd_environment.sv(47): (vlog-2730) Undefined variable: ‘env_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_environment.sv(47)
** at uvm_sd_environment.sv(47): (vlog-2730) Undefined variable: ‘env_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_environment.sv(47)
** at uvm_sd_environment.sv(47): (vlog-2730) Undefined variable: ‘env_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** while parsing macro expansion: ‘uvm_field_object’ starting at uvm_sd_environment.sv(47)
** at uvm_sd_environment.sv(47): (vlog-2730) Undefined variable: ‘env_cg’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** at uvm_sd_environment.sv(68): (vlog-2730) Undefined variable: ‘fsm_env_config’.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(17)
** at uvm_sd_environment.sv(74): Failed to find name ‘type_id’ in specified scope
** Error: ** while parsing file included at uvm_sd_allfiles.sv(20)
** at uvm_sd_tbtop.sv(19): near “module”: syntax error, unexpected module, expecting function or task
End time: 14:30:34 on Jul 19,2018, Elapsed time: 0:00:01
Errors: 14, Warnings: 0
[muthamizhselvi.m@chennai UVM_PROJECT]$
Actually what do these errors mean? Where should i correct them actually?
In reply to Muthamizh:
It looks loke your agent and env configurations are not visible in the compiled library.
Did you really compile the configurations and are they compile in the right order?
In reply to chr_sue:
yes, i have changed the order. Now I am getting these 2 errors.
** Error: ** while parsing file included at uvm_sd_allfiles.sv(18)
** at uvm_sd_environment.sv(76): Failed to find name ‘type_id’ in specified scope
** Error: ** while parsing file included at uvm_sd_allfiles.sv(20)
** at uvm_sd_tbtop.sv(19): near “module”: syntax error, unexpected module, expecting function or task
End time: 15:43:48 on Jul 19,2018, Elapsed time: 0:00:00
Errors: 2, Warnings: 0
In reply to Muthamizh:
Because I do not know what uvm_sd_allfiles.sv and uvm_sd_tbtop.sv is I can’t answer your question.
‘Failed to find name ‘type_id’ in specified scope’ points to a problem with the macros.
In reply to chr_sue:
//============================================================================
// CONFIDENTIAL and Copyright (C) 2010 Test and Verification Solutions Ltd
//============================================================================
// Contents : File for uvm_sd_tbtop.svh
//
// Brief description : Top file which runs the whole Environment
//
// Known exceptions to rules :
//
//============================================================================
// Author :
// Created on :
// File Id : uvm_sd_tbtop.sv
//============================================================================
ifndef UVM_SD_TBTOP_SV define UVM_SD_TBTOP_SV
module tb_top();
bit clk=1;
bit rst;
//clock generation
always #2 clk = ~clk;
//reset generation
initial
begin
rst=1;
#5 rst=0;
end
//Interface instance
intf vif(clk,rst);
//DUT instance
fsm1 DUT(.clk(vif.clk),
.rst(vif.rst),
.in(vif.in),
.out(vif.out),
.state(vif.state));
//Setting configuration database
initial
begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),“*”,“vif”,vif);
$dumpfile(“dump.vcd”);
$dumpvars;
end
initial
begin
run_test(“test”);
end
endmodule : tb_top
`endif
//COMPILE LIST
`include “uvm_macros.svh”
import uvm_pkg::*;
include "fsm1.sv" include “uvm_sd_interface.sv”
include "uvm_sd_seq_item.sv" include “uvm_sd_sequence.sv”
include "uvm_sd_sequencer.sv" include “uvm_sd_driver.sv”
include "uvm_sd_monitor.sv" include “uvm_sd_agent_config.sv”
include "uvm_sd_agent.sv" include “uvm_sd_scoreboard.sv”
include "uvm_sd_env_config.sv" include “uvm_sd_environment.sv”
include "uvm_sd_test.sv" include “uvm_sd_tbtop.sv”
these are those files
In reply to Muthamizh:
But I do not see the file ‘uvm_sd_allfiles.sv’ which is reported by the compiler.
In reply to chr_sue:
that is the compile list file name. i have sent that too, saying //COMPILE LIST
In reply to Muthamizh:
This is the eda link. Now i have got the output. But i dunno whether it is correct i.e is it compatible with the waveform??
In reply to Muthamizh:
You had a few weaknesses in your testbench. The most important is a $sformatf you do not need (appears twice)
use this uvm_info instead of yours using the $sformatf which was not correct
`uvm_info("VIF", {"virtual interface handle has been set for:",get_full_name(),".vif"},UVM_LOW)
Good simulators are reporting this weakness, but suppressing the error.
After a macro there is never a ‘;’
And finally using
`uvm_create
and
`uvm_send
is not really useful. Use instead the
`uvm_do
macro or work with
start_item/finish_item
.
It is now working.
See (3) - EDA Playground
In reply to chr_sue:
Thank you so much for your help. It was very useful. Now i need to create a testcase with 1001 overlapping patterned input. But am not sure, how to give that. if i should give constraints, how to constraint it or is there any other i could give patterned inputs? Could you please help me out on this?
In reply to Muthamizh:
I don’t understand why you need 1001 input pattterns …
But you can generate millions of patterns if needed by running an appropriate loop in your sequence.
The common apprach is to add constraints to your seq item and you can also add constarints (so-called control knobs) to your sequences.
I guess you need a certain number of sequences with different contraints to generate the patterns needed.
In reply to chr_sue:
how to create loops using constraints? thats what exactly i need to know… I mean the syntax.
In reply to Muthamizh:
in the body method of your sequence you can implement a loop like this
repeat (100)
`uvm_do_with(req, with {your constraints;})
In reply to chr_sue:
could me suggest me few corner testcases for fsm sequence detector uvm verification??
In reply to Muthamizh:
The absolut minimum is to verify all transitions from one state to another one.
In reply to chr_sue:
i want to check reset condition for my rtl. i.e while giving randomized inputs, i should apply reset in between, and all the fields should become zero when reset is 1. how to do that?