UVM

UVM
31

In reply to Muthamizh:

You had a few weaknesses in your testbench. The most important is a $sformatf you do not need (appears twice)
use this uvm_info instead of yours using the $sformatf which was not correct

`uvm_info("VIF", {"virtual interface handle has been set for:",get_full_name(),".vif"},UVM_LOW)

Good simulators are reporting this weakness, but suppressing the error.

After a macro there is never a ‘;’
And finally using

`uvm_create

and

`uvm_send

is not really useful. Use instead the

`uvm_do

macro or work with

start_item/finish_item

.

It is now working.
See (3) - EDA Playground

32

In reply to chr_sue:

Thank you so much for your help. It was very useful. Now i need to create a testcase with 1001 overlapping patterned input. But am not sure, how to give that. if i should give constraints, how to constraint it or is there any other i could give patterned inputs? Could you please help me out on this?

33

In reply to Muthamizh:

I don’t understand why you need 1001 input pattterns …
But you can generate millions of patterns if needed by running an appropriate loop in your sequence.
The common apprach is to add constraints to your seq item and you can also add constarints (so-called control knobs) to your sequences.
I guess you need a certain number of sequences with different contraints to generate the patterns needed.

34

In reply to chr_sue:

how to create loops using constraints? thats what exactly i need to know… I mean the syntax.

35

In reply to Muthamizh:

in the body method of your sequence you can implement a loop like this

repeat (100)
  `uvm_do_with(req, with {your constraints;})
36

In reply to chr_sue:

thank you so much. Thanks a lot.

37

In reply to chr_sue:

could me suggest me few corner testcases for fsm sequence detector uvm verification??

38

In reply to Muthamizh:

The absolut minimum is to verify all transitions from one state to another one.

39

In reply to chr_sue:

That i have done already. Any other test cases??

40

In reply to chr_sue:

i want to check reset condition for my rtl. i.e while giving randomized inputs, i should apply reset in between, and all the fields should become zero when reset is 1. how to do that?

41

In reply to Muthamizh:

Then you need an aidzional data member in your seq_item definition, indication in which disatnce the resets should appear.

42

In reply to chr_sue:

In my design, am resetting in top module. how to do that through seq item? I tried that, but it dint give me exact results. So how to do it properly?

43

In reply to Muthamizh:

All ports are available in your toplevel module. And these port signals are driven by the uvm_drivers. You can also drive the reset in your env. But you should not do this from an initial block in your toplevel module. This might not be coordinated with the function of thhe whole environment.

44

In reply to chr_sue:

Thats what am also confused about. Is there any possibility to do that by making changes in seq item? i did that but i dint get the exact output.

45

In reply to Muthamizh:

If you do not show how your implementation looks like I cannot give you an advice.

46

In reply to chr_sue:

This is how i tried doing it.

47

In reply to Muthamizh:

Any possible help for me??

48

In reply to Muthamizh:

instead of controlling reset from tb top, i want to do it through seq item. But somewhere i am missing out the connection. Could someone check that link and help me out??

49

In reply to Muthamizh:

This is one of the issues. The second one is rst is not rand in the seq_item definition.
And then you have to refine your driver with respect to the reset. the Reset function is mot usefula as it is now.

50

In reply to chr_sue:

I tried giving reset through seq item. but im missing out the logic in refining driver according to that. Can you tell how am i supposed to change the driver logic?