In reply to chr_sue:
Hi chr_sue,
- sequence_item is class extends from uvm_sequence_item.
- yes, am connected sequencer and driver in agent only
sequence_item is “req” declaration
sequence_item req;
Thanks,
In reply to Shivakumar AN:
Hi Shivakumar AN,
Ok i’ll remove that, but you have any other method?
because of port declaration mandatory right???
Thanks,
In reply to santosh vaddisetty:
Hi santosh vaddisetty,
yes santosh your correct ,am coded like that only but little bit change as follows
package my_pkg;
class sequenc_item extends from uvm_sequenc_item
…
…
endclass
…
…
class ac_lpc_driver extend from uvm_driver
…
…
endclass
endpackage
So can you tell me what wrong behind the code for that error.
Thanks,
In reply to Prawin kumar:
Hi Prawin,
seq_item_port is already declared in base class uvm_driver which you are extending from. So no need to declare it again in your ac_lpc_driver class.
Also you have declared it as analysis_port which is causing the error. get_next_item is a built in method of seq_item_port and not of analysis_port.
–
Regards,
Shivakumar
In reply to Prawin kumar:
Hi Shivakumar,
it’s compiled now, but with fatal error shown below,
code: if (!uvm_config_db#(virtual ac_lpc_if)::get(this, “”, “vif”, vif)) begin
`uvm_fatal(“ac_lpc_agent”, “No virtual interface specified for this agent instance”)
Error: uvm_test_top.env.agent [ac_lpc_agent] No virtual interface specified for this agent instance
Thanks,
In reply to Prawin kumar:
It seems there is no uvm_config_db set command from the toplevel module of your UVM testbench or you are limiting the access by specifying a wrong hierarchical Path in the set Command.
In reply to Prawin kumar:
If you want to retrieve a value from the config_db using the get command, you have to perform a set command to the config_db, to make sure there is a corresponding value in the config_db.
For the virtual interface the set will be done in the toplevel module of your UVM testbench.
In reply to chr_sue:
Hi,
Can you tell me why am getting this error?
function void build_phase(uvm_phase phase);
env = ac_lpc_env::type_id::create("env", this);
//test_seq = ac_lpc_tx_seq::type_id::create("test_seq",this);
sequencer = ac_lpc_sequencer::type_id::create("test_seq",this);
if(!uvm_config_db#(virtual ac_lpc_if)::get(this, "", "vif", vif)) begin
`uvm_fatal("ac_lpc_test", "No virtual interface specified for this test instance")
end
uvm_config_db#(virtual ac_lpc_if)::set( this, "env", "vif", vif);
endfunction
ERROR: uvm_test_top [ac_lpc_test] No virtual interface specified for this test instance.
Thanks,
In reply to Prawin kumar:
Hi Prawin,
You are getting this error because for every uvm_config_db get, there must be a corresponding set from the higher hierarchy. Looks like you have missed to set this interface from your TB Top. Please check for similar set code in your TB top:
uvm_config_db #(virtual ac_lpc_if)::set (null, “*”, “vif”, vif);
Also you can refer to some examples of set-get and complete UVM environment from below links. I would suggest you to go through these examples and videos.
- http://www.chipverify.com/uvm/top-module
- Simple but complete UVM example | Verification Academy
- Basic UVM | Universal Verification Methodology | Verification Academy
- Advanced UVM | Universal Verification Methodology | Verification Academy
–
Regards,
Shivakumar
In reply to Shivakumar AN:
Hi shiva,
I made it shiva but in driver am getting error again .
ERROR: uvm_test_top.env.driver [ac_lpc_driver] No virtual interface specified for this driver instance
Thanks,
In reply to Prawin kumar:
Can you try after changing
uvm_config_db#(virtual ac_lpc_if)::set( this, “env”, “vif”, vif);
to
uvm_config_db#(virtual ac_lpc_if)::set( this, “*”, “vif”, vif);
Giving * will make sure all the below hierarchy components can get from higher hierarchy.
Thanks,
Shivakumar
In reply to Shivakumar AN:
Hi,
before error in ‘test’ hierarchy
Now at ‘env’.
ERROR; uvm_test_top.env [ac_lpc_env] No virtual interface specified for this env instance.
In reply to Prawin kumar:
Hi,
Why this error is occurred?
task run_phase(uvm_phase phase);
ac_lpc_tx_seq test_seq;
phase.raise_objection(this, “starting test_seq”)
test_seq = ac_lpc_tx_seq::type_id::create(“test_seq”,this);
test_seq.start(env.agent.sequencer);
#100;
phase.drop_objection(this, “finished test_seq”);
endtask: run_phase
ERROR:“Incompatible types at assignment: .test_seq<ac_lpc_tx_seq>create(”“test_seq”“,this,”“”“)<uvm_sequence_item>.”"
Thanks,
In reply to Prawin kumar:
Looks a Little bit strange, because you never mentioned ‘test_seqcreate’.
My guess is your code does not look like this:
test_seq = ac_lpc_tx_seq::type_id::create(“test_seq”,this)
In reply to chr_sue:
Hi,
That is create method right,for test_seq.for rise and drop objection for sequence.
even though am getting error
E:“Incompatible types at assignment: .test_seq<ac_lpc_tx_seq> ← create(”“test_seq”“,this,”“”“)<uvm_sequence_item>.”
In reply to Prawin kumar:
Is the sequence compatible with the sequencer? It looks like it is not. Does the sequence generate the same seq_items as the sequencer is parameterized?
In reply to Prawin kumar:
Could you please provide the code for your test_seq and the corresponding sequencer.