Timescale difference between a Verilog file and a SystemVerilog file

SystemVerilog
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1

Hi,

I’m working on a project that has several Verilog and SystemVerilog files in it. There are 2 files in particular: one is the top-level file (top_tb.v), which contains the DUT, and also sends some stimulus to it; the other is the env file for the bench (tb_env.sv), which defines a class that extends vmm_env.

In the very beginning of both files, there is “`timescale 1ps/1ps”, so they should have the same timescale. However, according to my simulation result, doing a “#1000” in top_tb.v takes the same amount of time as doing a “#1” in tb_env.sv. Similarly, a “#1ns” in top_tb.v delays the same amount of time as a “1ps” in tb_env.sv.

I’m wondering if this difference comes from the fact that one of them is in Verilog and talks to the DUT, whereas the other is a SystemVerilog file.

Any thoughts is appreciated. Thanks.

2

In reply to coldler:

I also wonder after hearing this behavior! I am not sure why such behavior is occurring.

Would you try using timeunit & timeprecision in the module/class instead of compiler directive `timescale.
[Ref - 3.14.2.3 SV 2012 LRM]

3

In reply to Vinay Jain:

Thanks, Vinay. It might be the problem. I’m guessing the `timescale isn’t in effect when tb_env is instantiated; rather, the timescale of the file that instantiats tb_env is in effect. Thanks for your advice. I’ll try it and post the results later.

4

`timescale has no effect on items declared in the compilation unit (the area outside any module/interface/package.

You should be using timeunit withing SystemVerilog in order to avoid issues with `timescale ordering and defaults.

See 3.14.2.3 Precedence of timeunit, timeprecision, and `timescale of the IEEE 1800-2012 LRM

5

In reply to dave_59:

Thank you, Dave. I’m having some trouble understanding “compilation unit” and "compilation unit scope even after reading section 3.12.1 Compilation units.

The top_env.sv file is like this:

`timescale 1ps/1ps
class top_env extends vmm_env;
…
extern virtual task A();
endclass: topenv

task top_env::A();
…
#10;
endtask: A

program env_test;
top_env env;
initial begin
env = new;
…
end
endprogram: env_test

As shown above, I’m having a delay inside a task of a class. Would it mean that this delay will always use the default time unit because it’s not in a module/program/package/interface? Obviously it’s not using the timescale in the beginning of this file. I also tried to add timeunit and timeprecision in the beginning of program env_test, but it still doesn’t affect the delay in the class method. Where does the class method’s time unit and time precision get set?

6

In reply to coldler:

You class declaration is outside of a program/module/interface/package, therefore it is at the compilation unit level and `timescale is not applied and uses the default specified by your tool.

We strongly recommend that all class declarations go into a package

A few other recommendations for developing testbenches. You should not have any actual delays in your class based testbench - all delays should be handled by the interface or other modules connected to the DUT. If you must use a delay in your testbench, please add the appropriate time unit as in #10ns. having a plain #10 is very error prone.

7

In reply to dave_59:

Thanks for the answer and the useful tips.

8

In reply to coldler:

Hi Vinay, even adding timeunit and timescale didn’t work so well for me. As dave_59 said, “Your class declaration is outside of a program/module/interface/package, therefore it is at the compilation unit level and `timescale is not applied and uses the default specified by your tool.” I also don’t think I’m allowed to add timeunit or timeprecision in my class declaration.