Timescale difference between a Verilog file and a SystemVerilog file

In reply to coldler:

You class declaration is outside of a program/module/interface/package, therefore it is at the compilation unit level and `timescale is not applied and uses the default specified by your tool.

We strongly recommend that all class declarations go into a package

A few other recommendations for developing testbenches. You should not have any actual delays in your class based testbench - all delays should be handled by the interface or other modules connected to the DUT. If you must use a delay in your testbench, please add the appropriate time unit as in #10ns. having a plain #10 is very error prone.