Timescale difference between a Verilog file and a SystemVerilog file

In reply to dave_59:

Thank you, Dave. I’m having some trouble understanding “compilation unit” and "compilation unit scope even after reading section 3.12.1 Compilation units.

The top_env.sv file is like this:

`timescale 1ps/1ps
class top_env extends vmm_env;

extern virtual task A();
endclass: topenv

task top_env::A();

#10;
endtask: A

program env_test;
top_env env;
initial begin
env = new;

end
endprogram: env_test

As shown above, I’m having a delay inside a task of a class. Would it mean that this delay will always use the default time unit because it’s not in a module/program/package/interface? Obviously it’s not using the timescale in the beginning of this file. I also tried to add timeunit and timeprecision in the beginning of program env_test, but it still doesn’t affect the delay in the class method. Where does the class method’s time unit and time precision get set?