Timescale difference between a Verilog file and a SystemVerilog file

SystemVerilog
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2

In reply to coldler:

I also wonder after hearing this behavior! I am not sure why such behavior is occurring.

Would you try using timeunit & timeprecision in the module/class instead of compiler directive `timescale.
[Ref - 3.14.2.3 SV 2012 LRM]