I have three values which are signed logic vectors as shown below. I am trying to build a constraint where the sum of the three numbers, positive and negative included should be less than a constant.

parameter signed LIMIT = 200;
rand logic signed [15:0] a;
rand logic signed [15:0] b;
rand logic signed [15:0] c;

constraint limit {a+b+c < LIMIT);

I tried the above code snippet but it does not obey the constraint.I would like the value of a ,b and c be negative/and or positive but the sum to be less than the constant.

I am not certain how the parameter is interpreted internally
( As Signed OR Unsigned ?? .
I believe LRM isn’t clear about this so the result might vary across Simulators !! )

Verilog Basics dictate ::
If it’s signed the each Operand in the expression would be treated as Signed , else Each Operand would be treated as Unsigned !!

It would be easier to analyze if you had posted the results too

parameter is being treated as signed. I had actually defined it as follows. (Typo in my original post)

parameter signed LIMIT = 200;

I do see that the values for a,b and c are getting randomized between negative and positive numbers. But its just that the sum of the three numbers seems to violate the value of LIMIT.

Sorry should have been clear. The LIMIT is a parameter and I had it parameterized to 3 hex. I made the following changes and it seems to work well now.

parameter signed LIMIT = 200;
rand logic signed [15:0] a;
rand logic signed [15:0] b;
rand logic signed [15:0] c;