SystemVerilog Constraint Help for Negative/Postiive numbers

In reply to kk9110:

I believe there could be a misinterpretation on your part .
Realize if the MSb of a , b , c are 1’b1 , they indicate Negative Numbers !!

One could read it as unsigned ( which isn’t true )

What’s the sum you Observe ? Also How are you displaying / Calculating the sum ?