SystemVerilog Constraint Help for Negative/Postiive numbers

In reply to ABD_91:

parameter is being treated as signed. I had actually defined it as follows. (Typo in my original post)

parameter signed LIMIT = 200;

I do see that the values for a,b and c are getting randomized between negative and positive numbers. But its just that the sum of the three numbers seems to violate the value of LIMIT.