In reply to kk9110:
I am not certain how the parameter is interpreted internally
( As Signed OR Unsigned ?? .
I believe LRM isn’t clear about this so the result might vary across Simulators !! )
Verilog Basics dictate ::
If it’s signed the each Operand in the expression would be treated as Signed ,
else Each Operand would be treated as Unsigned !!
It would be easier to analyze if you had posted the results too