SystemVerilog Constraint Help for Negative/Postiive numbers

In reply to kk9110:

Besides the ‘signed’ keyword I believe you have changed the Packed Dimensions too in Original Code !!

[ Previously it was [7:0] for all 3 Variables . ]

Anyways with [15:0] there are Chances of Overflow too .

(1) Also LIMIT is 200 which is 32-bit Signed .
(200) in Decimal is (C8) in hexadecimal .

Why are you expecting it to be 3H ??

(2) Try to display all 3 Variables in “%0d” Format String