SVA for AHB protocol violations - Read bus should not get data when write transaction is going on

SystemVerilog
,
2

In reply to sanjay864u:

Sanjay,
It’s happening due to 1:$ in the antecedent. What you need is something like below:


  vw_no_rd_during_wr : assert property (@(posedge clk) disable iff (rst) 
   (hsel & hwrite && hready |=> $stable(hrdata)
   else
     `uvm_error("CIP", "hrdata changed during a write transfer");

HTH
Srini
www.verifworks.com