SVA for AHB protocol violations - Read bus should not get data when write transaction is going on

user60 · November 8, 2016, 8:50am

In reply to sanjay864u:

Sanjay,
As far as I recall in AHB, control signal like heel, write shall remain constant during wait state, hence my simple logic of:

hsel && hwrite && hready

Should work in this case. And I suggest you use logical AND only, though in this example it may not make a difference (See: Verification Course Blog | VeriLog Courses | CVC).

I used $stable(hrdata) as I don’t recall AHB spec saying rdata shall be ZERO during write transfer - do you have a spec pointer for this?