SVA for AHB protocol violations - Read bus should not get data when write transaction is going on

SystemVerilog
,
6

In reply to kddholak:

Hi,

With the below code the assertion did not fail for a single time also.

vw_no_rd_during_wr : assert property (@(posedge clk) disable iff (rst)
(hsel & hwrite) |-> hrready[->1] ##0 (hrdata==0);
else
`uvm_error(“CIP”, “hrdata changed during a write transfer”);

thanks & regards,
sanjoy