I did not get the use of logical and bit wise and operation.
hsel & hwrite && hready
Also, if the slave does not return the HREADY at the very next cycle after HSEL and HWRITE, then how the above part of code will work? It may happen the slave is not ready to take the HWDATA.
In reply to sanjay864u:
Hello Sanjoy
When there is write on the bus , and hready can go high in certain delay. when it goes high hrdata should be zero.
Yes, for the address phase my above code should do the job for you. For extended data phases (waits, splits etc.) you will need some custom logic to indicate pending wait_xfer and use that signal in a similar property.
According to AHB specification, value on HRDATA does not matter when WRITE transaction is going on. This assertion might be fine with your design, but it’ll throw unnecessary errors with other AHB compliant designs.
As per AHB spec, HRDATA should be stable during WRITE transaction as Srini Sir mentioned in last comment.
If it happens then it is a protocol violation.
Moreover, in case of protected transfer if this happens the the protected data may come to the bus which hackers can easily get.
This kind of checks must be present in AHB AVIP.