SVA for AHB protocol violations - Read bus should not get data when write transaction is going on

SystemVerilog
,
5

In reply to sanjay864u:
Hello Sanjoy
When there is write on the bus , and hready can go high in certain delay. when it goes high hrdata should be zero.


 vw_no_rd_during_wr : assert property (@(posedge clk) disable iff (rst) 
   (hsel & hwrite) |-> hrready[->1] ##0 (hrdata==0);
   else
     `uvm_error("CIP", "hrdata changed during a write transfer");