SVA for AHB protocol violations - Read bus should not get data when write transaction is going on

SystemVerilog
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8

In reply to Srini @ CVCblr.com:

Hi Srini Sir,

The HSEL and HWRITE remain constant in case of address phase, once the address is decoded the HREADY may go low from slave and prolong the data phase.

And $stable(hrdata) is fine as per spec, I used (hrdata==0) for my application purpose.

thanks & regards,
sanjoy