SVA for AHB protocol violations - Read bus should not get data when write transaction is going on

SystemVerilog
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3

In reply to Srini @ CVCblr.com:

Hi Srini Sir,

I have a few queries on the above code.

  1. I did not get the use of logical and bit wise and operation.
    hsel & hwrite && hready

  2. Also, if the slave does not return the HREADY at the very next cycle after HSEL and HWRITE, then how the above part of code will work? It may happen the slave is not ready to take the HWDATA.

Thanks & regards,
sanjoy