Question: Verification should apply an assertion check for setup and hold of 10 functional clocks between data and strobe.
I tried writing Following code, this is how I have written this question in code but I am getting following error(hint consequent of property hold_checker may be the reason for error )
Error-[SVA-SEQPROPEMPTYMATCH] Invalid sequence as property
/vobs/asic_adc_dac_testchip/hydra_t/SE/assertions/hydra_t_strobe_assertions.sv, 65
“($stable(data) [* HOLD_TIME])”
A sequence that is used as property must be non-degenerate and admit no
empty match.
NOTE: I would really appreciate if some could help me with this it would be a great learning for me.
`timescale 1ns/1ps
import uvm_pkg::*;
`include “uvm_macros.svh”
module DAC_ADC_Analog_Timing_checker( clk_in,strb_in, resetn, disable_assertion, data );
parameter SETUP_TIME = 3; // this vale will be passed from binding module which is written in the code below
parameter HOLD_TIME = 6; // this vale will be passed from binding module which is written in the code below
parameter CK_PERIOD = 1;
// parameter CK_EDGE_SEL = 1’b1; // 0: posedge, 1: negedge
define adc_wrapper_path hydra_t_hdl_top.dut.analog_adc_wrapper_inst define ADC_ANALOG_PATH hydra_t_hdl_top.dut.analog_adc_wrapper_inst.HYDRA_TADC_ANALOG_inst
define DAC_ANALOG_PATH hydra_t_hdl_top.dut.analog_dac_wrapper_inst.HYDRA_TDAC_ANALOG_inst define DAC_NCO_ANALOG_PATH hydra_t_hdl_top.dut.analog_dac_wrapper_inst.HYDRA_TNCO_ANALOG_inst
input clk_in;
input strb_in;
input resetn;
input disable_assertion;
input [63:0] data;
//=================================================
// Property Specification Layer
//=================================================
property hold_checker;
@(posedge clk_in)
disable iff (~resetn || disable_assertion)
$rose(strb_in) |-> ($stable(data)[*HOLD_TIME]); // Consequent is the reason i gueess for the error
endproperty
property setup_checker;
@(posedge clk_in)
disable iff (~resetn || disable_assertion)
$changed(data)|-> !strb_in[*SETUP_TIME];
endproperty
//=================================================
// This is how you use “assert”
//=================================================
setup_checker_Assert: assert property (setup_checker) $display($stime,"\t Pass :: Assertion passes setup_checker ");
else `ASSERT_ERROR( $sformatf("Fail :: Assertion fail the setup_checker "))
hold_checker_Assert: assert property (hold_checker) $display($stime,"\t Pass :: Assertion passes hold_checker ");
else `ASSERT_ERROR( $sformatf("Fail :: Assertion fail the hold_checker "))
//=================================================
// This is how you use “cover”
//=================================================
setup_checker_Assert_cover : cover property (setup_checker);
hold_checker_Assert_cover : cover property (hold_checker);
endmodule : DAC_ADC_Analog_Timing_checker
//--------------------------------------------------------------------------------------------------------------------
// Binding ADC module
//--------------------------------------------------------------------------------------------------------------------
module tadc_strobe_bindings;
define ADC_IF_PATH hydra_t_hdl_top.itf.misc_itf define ASSERT_ON
`ifdef ASSERT_ON
// ADC Fractional DLL interface
//Functional CLK (447.300 MHz)
//Type 1
bind `ADC_ANALOG_PATH DAC_ADC_Analog_Timing_checker
#(.CK_EDGE_SEL (1’b1), .SETUP_TIME(2), .HOLD_TIME(2)) ADC_fs144PHROT_STRB_checker(
.clk_in(`ADC_ANALOG_PATH.o_refck) ,
.strb_in(`ADC_ANALOG_PATH.i_fs144_phrot_strb_n),
.resetn(`ADC_ANALOG_PATH.i_resetn),
.disable_assertion(!`ADC_IF_PATH.en_global_assertion),
.data({
54'd0,
`ADC_ANALOG_PATH.iv_fs144_phrot[9:0]
})
);
endtadc_strobe_bindings
