Regarding the assertion checking for setup and hold between strb and data

SystemVerilog
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5 
*<font size=12>In reply to [ben@SystemVerilog.us](/forums/t/regarding-the-assertion-checking-for-setup-and-hold-between-strb-and-data/35197/4):</font>*

sir can we use if else in property, I did something as follows but it gives an error ? 

**code as follows**

[code]
property hold_checker;
   @(posedge clk_in)
   disable iff (~resetn || disable_assertion)
   
    	if(CK_EDGE_SEL)   
    	  begin
            $fell(strb_in)  |-> ##0 $stable(data)[*HOLD_TIME] //<-- use semicolon yes/no ?    
          end 
	 
	else    	 
	  begin
	    $rose(strb_in)  |-> ##0 $stable(data)[*HOLD_TIME];  
	  end 
endproperty