In reply to ben@SystemVerilog.us:
I apologize for asking the questions again and again
- I am getting following warning when I am simulating the following properties i have to use ##0 at |-> ##0 $stable(data)[*HOLD_TIME]; otherwise its giving ERROR refer ERROR 1
- I am stuck in this loop and I am not understanding how to come out of this problem…?
- And when i am covering property how can i check it i am using DVE
- I would be a great learning to overcome this problem.
NOTE: I am using VCS simulator /opt/tools/tools/VCS_MXi/v_2017.12/bin/vcs
ERROR 1:
Error-[SVA-SEQPROPEMPTYMATCH] Invalid sequence as property
/vobs/asic_adc_dac_testchip/hydra_t/SE/assertions/hydra_t_strobe_assertions.sv, 114
“($stable(data) [* HOLD_TIME])”
A sequence that is used as property must be non-degenerate and admit no
empty match.
Warning Messages
Warning-[SVA-AITT] Unsatisfiable sequence in assertion
/vobs/asic_adc_dac_testchip/hydra_t/SE/assertions/hydra_t_strobe_assertions.sv, 117
Please note that assertion hold_checker_rose_Assert contains an
unsatisfiable sequence. The assertion may thus be either trivially true or
trivially false. It will not be simulated.
property hold_checker_fell;
@(posedge clk_in)
disable iff (!resetn || disable_assertion)
##1 CK_EDGE_SEL && $fell(strb_in) |-> $stable(data)[*HOLD_TIME];
//$fell(strb_in) |-> ##0 $stable(data)[*HOLD_TIME]; //local_hold_seq; //($stable(data)[*3]);
//$rose(strobe) (temp=data)|-> (data==temp)[*10]
endproperty
property hold_checker_rose;
@(posedge clk_in)
disable iff (!resetn || disable_assertion)
##1 !CK_EDGE_SEL && $rose(strb_in) |-> ##0 $stable(data)[*HOLD_TIME];
//$fell(strb_in) |-> ##0 $stable(data)[*HOLD_TIME]; //local_hold_seq; //($stable(data)[*3]);
//$rose(strobe) (temp=data)|-> (data==temp)[*10]
endproperty
property setup_checker_fell;
@(posedge clk_in)
disable iff (!resetn || disable_assertion)
##1 CK_EDGE_SEL && $fell(strb_in) |-> ##0 $past(data)[*SETUP_TIME];
//$fell(strb_in) |-> ##0 $past(data)[*SETUP_TIME] ;
//$changed(data)|-> ##0 !(strb_in)[*SETUP_TIME];
endproperty
property setup_checker_rose;
@(posedge clk_in)
disable iff (!resetn || disable_assertion)
##1 !CK_EDGE_SEL && $rose(strb_in) |-> ##0 $past(data)[*SETUP_TIME];
//$fell(strb_in) |-> ##0 $past(data)[*SETUP_TIME] ;
//$changed(data)|-> ##0 !(strb_in)[*SETUP_TIME];
endproperty
//=================================================
// This is how you use "assert" $display($stime,"\t Pass :: Assertion passes hold_checker ");
//=================================================
hold_checker_fell_Assert: assert property (hold_checker_fell) $display("time:%t assertion passed hold_checker_fell",$time);
else `ASSERT_ERROR( $sformatf("Fail :: Assertion fail the hold_checker_fell "))
hold_checker_rose_Assert: assert property (hold_checker_rose) $display("time:%t assertion passed hold_checker_rose",$time);
else `ASSERT_ERROR( $sformatf("Fail :: Assertion fail the hold_checker_rose "))
setup_checker_fell_Assert: assert property (setup_checker_fell) $display($stime,"\t Pass :: Assertion passes setup_checker_fell ");
else`ASSERT_ERROR( $sformatf("Fail :: Assertion fail the setup_checker_fell "))
setup_checker_rose_Assert: assert property (setup_checker_rose) $display($stime,"\t Pass :: Assertion passes setup_checker_rose ");
else`ASSERT_ERROR( $sformatf("Fail :: Assertion fail the setup_checker_rose "))
//=================================================
// This is how you use "cover"
//=================================================
hold_checker_fell_Assert_cover : cover property (hold_checker_fell);
hold_checker_rose_Assert_cover : cover property (hold_checker_rose);
setup_checker_fell_Assert_cover: cover property (setup_checker_fell);
setup_checker_rose_Assert_cover: cover property (setup_checker_rose);