In reply to venkatasubbarao:
Looking at just the syntax, your code is OK; it compiles and elaborates OK.
BTW, when you post code, use the
angle_bracket_here systemverilog] CODE GOES HERE /angle_bracket_here slash systemverilog]
`timescale 1ns/1ps
import uvm_pkg::*; `include "uvm_macros.svh"
module DAC_ADC_Analog_Timing_checker( clk_in,strb_in, resetn, disable_assertion, data );
parameter SETUP_TIME = 3; // this vale will be passed from binding module which is written in the code below
parameter HOLD_TIME = 6; // this vale will be passed from binding module which is written in the code below
parameter CK_PERIOD = 1;
// parameter CK_EDGE_SEL = 1'b1; // 0: posedge, 1: negedge
`define ASSERT_ERROR $error
`define adc_wrapper_path hydra_t_hdl_top.dut.analog_adc_wrapper_inst
`define ADC_ANALOG_PATH hydra_t_hdl_top.dut.analog_adc_wrapper_inst.HYDRA_TADC_ANALOG_inst
`define DAC_ANALOG_PATH hydra_t_hdl_top.dut.analog_dac_wrapper_inst.HYDRA_TDAC_ANALOG_inst
`define DAC_NCO_ANALOG_PATH hydra_t_hdl_top.dut.analog_dac_wrapper_inst.HYDRA_TNCO_ANALOG_inst
input clk_in;
input strb_in;
input resetn;
input disable_assertion;
input [63:0] data;
//=================================================
// Property Specification Layer
//=================================================
property hold_checker;
@(posedge clk_in)
disable iff (~resetn || disable_assertion)
$rose(strb_in) |-> ($stable(data)[*HOLD_TIME]);
// Consequent is the reason i gueess for the error
endproperty
property setup_checker;
@(posedge clk_in)
disable iff (~resetn || disable_assertion)
$changed(data)|-> !strb_in[*SETUP_TIME];
endproperty
//=================================================
// This is how you use "assert"
//=================================================
setup_checker_Assert: assert property (setup_checker) $display($stime,"\t Pass :: Assertion passes setup_checker ");
else `ASSERT_ERROR( $sformatf("Fail :: Assertion fail the setup_checker "));
hold_checker_Assert: assert property (hold_checker) $display($stime,"\t Pass :: Assertion passes hold_checker ");
else `ASSERT_ERROR( $sformatf("Fail :: Assertion fail the hold_checker "));
//=================================================
// This is how you use "cover"
//=================================================
setup_checker_Assert_cover : cover property (setup_checker);
hold_checker_Assert_cover : cover property (hold_checker);
endmodule : DAC_ADC_Analog_Timing_checker
//--------------------------------------------------------------------------------------------------------------------
// Binding ADC module
//--------------------------------------------------------------------------------------------------------------------
/*
module tadc_strobe_bindings;
`define ADC_IF_PATH hydra_t_hdl_top.itf.misc_itf
`define ASSERT_ON
`ifdef ASSERT_ON
// ADC Fractional DLL interface
//Functional CLK (447.300 MHz)
//Type 1
bind `ADC_ANALOG_PATH DAC_ADC_Analog_Timing_checker
#(.CK_EDGE_SEL (1'b1), .SETUP_TIME(2), .HOLD_TIME(2)) ADC_fs144PHROT_STRB_checker(
.clk_in(`ADC_ANALOG_PATH.o_refck) ,
.strb_in(`ADC_ANALOG_PATH.i_fs144_phrot_strb_n),
.resetn(`ADC_ANALOG_PATH.i_resetn),
.disable_assertion(!`ADC_IF_PATH.en_global_assertion),
.data({
54'd0,
`ADC_ANALOG_PATH.iv_fs144_phrot[9:0]
})
);
endtadc_strobe_bindings */
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
- http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
- “Using SVA for scoreboarding and TB designs”
http://systemverilog.us/papers/sva4scoreboarding.pdf - “Assertions Instead of FSMs/logic for Scoreboarding and Verification”
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3 - SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment