Regarding the assertion checking for setup and hold between strb and data

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Thank you very much for your response, this is my first time posting on forums I will keep that in mind.

if my code is correct then, how can I make a directed test so that I can pass and fail just to test the specification works according to the property following is my code


//=================================================
// Drive the input vectors to test assetion
//=================================================
initial begin
  // Init all the values
  resetn <= 0;
  strb_in<= 0;
  data <= 0;

// Cause assertion to pass  
repeat(10)  @(posedge clk_in);
  strb_in <= 1;
repeat(10)@ (posedge clk_in);
  strb_in <= 0;
  

// Cause assertion to fail
repeat(20)  @ (posedge clk_in);
  strb_in <= 1;
  repeat(2) @ (posedge clk_in);
  strb_in <= 1;
  
  #1000 $finish;
end
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