How to use ==? in system verilog

SystemVerilog
1

Can you explain the working of “==?” in

                                   if(stage ==? 6'b1??1??)
                                               //block of statements
                                   end

stage is enum

2

In reply to asreeraj:

In general the wildcard comparison operator is used to make few bits in RHS as don’t-cares. The syntax you show above - is it part of casez/casex?

Regards
Srini
www.verifworks.com

3

In reply to asreeraj:
Assume stage was declared with a typedef:

typedef enum logic [5:0] {S1=6'b100100, S2=6'b100111,S3=6'b100000} stage_e;

Then (stage ==? 6’b1??1??) would be true if stage had the value S1 or S2, and false for the value S3. If stage had the uninitialized value 6’bx, it would evaluate to false.

4

In reply to dave_59:

Thanks Dave. Can you name the operator ==?

5

In reply to asreeraj:

Table 7-1: Wild equality and wild inequality operators
SystemVerilog_3.1aLRM

Operator :: Usage :: Description
=?= :: a =?= b :: a equals b, X and Z values act as wild cards
!?= :: a !?= b :: a not equal b, X and Z values act as wild cards

6

In reply to Ravi Nagadia:

Thanks Ravi

7

In reply to dave_59:

Hi Dave,


  logic [2:0] j1 = 3'bxxx;
  logic [2:0] j2 = 3'bzz1;
  logic  j3;
  j3 = (j1==?j2);
  $display("j3 = %0b",j3);


Output ::

# j3 = x
# ** Note: $finish    : top.v(45)
#    Time: 1050 ns  Iteration: 0  Instance: /top
# End time: 10:45:40 on Jan 06,2017, Elapsed time: 0:00:01
# Errors: 0, Warnings: 7

In LRM :: The =?= and !?= operators treat X or Z as wild cards that match any value, thus, they too never result in X.

I am using questa 10.4c
I hope it resolved in latest releases.

8

In reply to Ravi Nagadia:

In reply to dave_59:
In LRM :: The =?= and !?= operators treat X or Z as wild cards that match any value, thus, they too never result in X.

The LRM does not say that. It does say

The == and != operators may result in x if any of their operands contains an X or Z. The**===** and !== operators explicitly check for 4-state values; therefore, X and Z values shall either match or mismatch, never resulting in X. The ==? and !=? operators may result in X if the left operand contains an x or Z that is not being compared with a wildcard in the right operand.

An X in a conditional if statement is treated as false.

9

In reply to dave_59:

Thanks Dave,

got it, only right operand x or Z would consider as wildcard.