How to use ==? in system verilog

SystemVerilog
7

In reply to dave_59:

Hi Dave,


  logic [2:0] j1 = 3'bxxx;
  logic [2:0] j2 = 3'bzz1;
  logic  j3;
  j3 = (j1==?j2);
  $display("j3 = %0b",j3);


Output ::

# j3 = x
# ** Note: $finish    : top.v(45)
#    Time: 1050 ns  Iteration: 0  Instance: /top
# End time: 10:45:40 on Jan 06,2017, Elapsed time: 0:00:01
# Errors: 0, Warnings: 7

In LRM :: The =?= and !?= operators treat X or Z as wild cards that match any value, thus, they too never result in X.

I am using questa 10.4c
I hope it resolved in latest releases.