How to use ==? in system verilog

SystemVerilog
5

In reply to asreeraj:

Table 7-1: Wild equality and wild inequality operators
SystemVerilog_3.1aLRM

Operator :: Usage :: Description
=?= :: a =?= b :: a equals b, X and Z values act as wild cards
!?= :: a !?= b :: a not equal b, X and Z values act as wild cards