How to make a constraint with implication to be soft constraint

SystemVerilog
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1

Hi All,

I am trying to configure an implication constraint to be soft constraint, but i always got compilation error when i add the keyword soft.

For example, the following code can execute without problem.


class packet;
  rand bit [3:0] addr;
       string    addr_range;
  
  constraint address_range { (addr_range == "small") -> (addr < 8);}

endclass

However, once I add “soft”, I’ll got compilation error.


class packet;
  rand bit [3:0] addr;
       string    addr_range;
  
  constraint address_range { soft (addr_range == "small") -> (addr < 8);}

endclass

Error-[SE] Syntax error
Following verilog source has syntax error :
“testbench.sv”, 8: token is ‘->’
constraint address_range { soft (addr_range == “small”) → (addr < 8);}

Wonder what should i do to make this constraint soft?

Thanks in advance!

Hao

2

In reply to peterjin:

You need a newer tool. This was clarified to be legal in the 1800-2017 LRM. From section 18.5.14 Soft constraints:

class Packet;
  rand bit mode;
  rand int length;
  constraint deflt {
  soft length inside {32,1024};
  soft mode -> length == 1024;
  // Note: soft mode -> {length == 1024;} is not legal syntax,
  // as soft must be followed by an expression
  }
endclass
3

In reply to dave_59:

Thanks so much for your help!

Hao

4

In reply to dave_59:

Hi Dave,

Is the following constraint allowed:

soft mode -> ((length <== 1024) && (length != 500));

Thanks,
Madhu

5

In reply to mseyunni:

No. You need to write this as

mode -> soft ((length <== 1024) && (length != 500));

or don’t use the implication operator

soft (!mode || (length <== 1024) && (length != 500) )
6

In reply to dave_59:

Thank you Dave.